1. Field of the Invention
This invention relates to a liquid crystal display and fabricating method thereof, and more particularly to a liquid crystal display that obtains the capacitance of a storage capacitor while increasing the aperture ratio.
2. Description of the Related Art
Generally, a liquid crystal display (LCD) controls the light transmittance of liquid crystal cells in response to a video signal to thereby display a picture. An active matrix LCD having a switching device for each liquid crystal cell is suitable for displaying a moving picture. The active matrix LCD mainly uses a thin film transistor (TFT) as the switching device.
The LCD uses a storage capacitor for the purpose of sustaining the voltage drop across the liquid crystal to assure the stability of a gray level display. The storage capacitor is classified into a storage on gate (SOG) system that overlaps a portion of the (n-1)th gate line with the nth pixel electrode to form a storage capacitor of the nth pixel, and a storage on common (SOC) system that provides a separate common electrode at the lower portion of a pixel electrode to form a storage capacitor.
FIG. 1 is a plan view showing a structure of an array substrate of a conventional LCD adopting a storage on gate system, and FIG. 2 is a section view of the array substrate taking along the A-A′ line in FIG. 1.
Referring to FIG. 1 and FIG. 2, a lower substrate 11 of the LCD includes a TFT arranged at an intersection between a gate line 15′ and a data line 17. A pixel electrode 33 is connected to a drain electrode 27 of the TFT, and a storage capacitor is positioned at an overlapping portion between the pixel electrode 33 and the pre-stage gate line 15.
The TFT includes a gate electrode 13 connected to the gate line 15′, a source electrode 25 connected to the data line 17, and a drain electrode 27 connected, via a first contact hole 30a, to the pixel electrode 33. Further, the TFT includes a gate insulating film 19 for insulating the gate electrode 13 and the source and drain electrodes 25 and 27, and semiconductor layers 21 and 23 for defining a conduction channel between the source electrode 25 and the drain electrode 27 by a gate voltage applied to the gate electrode 13. Such a TFT responds to a gate signal from the gate line 15′ to selectively apply a data signal from the data line 17 to the pixel electrode 33.
The pixel electrode 33 is positioned at a cell area divided by the data line 17, and the gate line 15′ and is made from a transparent conductive material having a high light transmittance. The pixel electrode 33 is provided on a protective film 31 coated on the entire surface of the lower substrate 11 and is electrically connected, via the first contact hole 30a defined in the protective film 31, to the drain electrode 27. The pixel electrode 33 generates a potential difference from a common transparent electrode (not shown) provided at an upper substrate (not shown) by a data signal applied via the TFT. This potential difference allows a liquid crystal positioned between the lower substrate 11 and the upper substrate (not shown) to change the liquid crystalline molecular arrangement in accordance with its dielectric anisotropy. Accordingly, an arrangement of the liquid crystal molecules is changed for each pixel in accordance with a data voltage applied via the TFT, thereby expressing pictorial information on the LCD.
The storage capacitor should have a capacitance value large enough to maintain a stable pixel voltage. To this end, the storage capacitor includes a capacitor electrode 29 electrically connected, via a second contact hole 30b, to the pixel electrode, and a gate line 15 having a gate insulating film 19 therebetween.
FIG. 3A to FIG. 3E are section views for explaining a method of fabricating the array substrate of the LCD shown in FIG. 2.
Referring first to FIG. 3A, the gate electrode 13 and the gate line 15 are provided on the substrate 11. The gate electrode 13 and the gate line 15 are formed by depositing aluminum (Al) copper (Cu) or other suitable materials by using a deposition technique such as sputtering, and then patterning it.
Referring to FIG. 3B, the gate insulating film 19, an active layer 21 and an ohmic contact layer 23 are provided. The gate insulating film 19 is formed by depositing an insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx) using a plasma enhanced chemical vapor deposition (PECVD) technique in such a manner as to cover the gate electrode 13 and the gate line 15.
The active layer 21 and the ohmic contact layer 23 are formed by sequentially disposing two semiconductor layers on the gate insulating film 19 and then patterning the disposed semiconductor layers. The active layer 21 is formed from amorphous silicon that is not doped with an impurity. On the other hand, the ohmic contact layer 23 is formed from amorphous silicon doped with an n-type or p-type impurity at a high concentration.
Referring to FIG. 3C, the data line 17, the source and drain electrodes 25 and 27 and the capacitor electrode 29 are provided on the gate insulating film 19. The data line 17, the source and drain electrodes 25 and 27 and the capacitor electrode 29 are formed by entirely depositing a metal layer using a CVD technique or a sputtering technique and then patterning. After the source and drain electrodes 25 and 27 were patterned, the ohmic contact layer 23 at an area corresponding to the gate electrode 13 is patterned to expose the active layer 21. The area of the active layer 21 corresponding to the gate electrode 13 between the source and drain electrodes 25 and 27 makes a channel. The capacitor electrode 29 overlaps with the gate line 15. The data line 17, the source and drain electrodes 25 and 27 and the capacitor electrode 29 are made from chromium (Cr) or molybdenum (Mo).
Referring to FIG. 3D, a protective layer 31 having first and second contact holes 30a and 30b is provided. The protective layer 31 is formed by depositing an insulating material on the gate insulating layer 19 and then patterning it in such a manner to cover the source and drain electrodes 25 and 27. The protective layer 31 is mainly made from an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx).
Referring to FIG. 3E, a pixel electrode 33 is provided on the protective film 31. The pixel electrode 33 is formed by depositing a transparent conductive material on the protective film 31 and then patterning it. The pixel electrode 33 is electrically connected, via the first contact hole 30a, to the drain electrode 27 and is electrically connected, via the second contact hole 30b, to the capacitor electrode 29. The pixel electrode 33 is made from a transparent conductive material that can be indium-tin-oxide (ITO), indium-zinc-oxide (IZO) or indium-tin-zinc-oxide (ITZO).
FIG. 4 is a plan view showing a structure of an array substrate of a conventional LCD having storage on a common system. FIG. 5 is a sectional view of the array substrate taking along the B-B′ line in FIG. 4.
In this storage on common system, a storage capacitor is positioned at the center of a pixel area. The storage capacitor should have a capacitance value large enough to maintain a stable pixel voltage. To this end, the storage capacitor has a pixel electrode 55 electrically connected to a drain electrode 59, and a capacitor common electrode 45 having a gate insulating film 49 therebetween.
FIG. 6A to FIG. 6D are section views for explaining the method steps of fabricating the array substrate of the LCD shown in FIG. 5.
Referring to FIG. 6A, the gate electrode 43, the capacitor electrode 45 and the gate line 47 are provided on the substrate 41. The gate electrode 43, the capacitor electrode 45 and the gate line 47 are formed by depositing aluminum (Al), copper (Cu) or other suitable material by using a deposition technique, preferably sputtering, and then patterning.
Referring to FIG. 6B, the gate insulating film 49, an active layer 51 and an ohmic contact layer 53 are provided. The gate insulating film 49 is formed by depositing an insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx) using a plasma enhanced chemical vapor deposition (PECVD) technique so as to cover the gate electrode 43, the capacitor common electrode 45 and the gate line 47.
The active layer 51 and the ohmic contact layer 53 are formed by sequentially disposing two semiconductor layers on the gate insulating film 49 and then patterning the disposed semiconductor layers. The active layer 51 is formed from undoped amorphous silicon. On the other hand, the ohmic contact layer 53 is formed from amorphous silicon doped with a high concentration of an N-type or P-type impurity.
Referring to FIG. 6C, a pixel electrode 551 the data line 63 and source and drain electrodes 57 and 59 are provided on the gate insulating film 49. The pixel electrode 55 is formed by depositing a transparent conductive material on the gate insulating film 49 and then patterning it. The pixel electrode 55 is made from any one of ITO, IZO and ITZO.
Subsequently, the data line 63 (see FIG. 4) and the source and drain electrodes 57 and 59 are provided. The data line 63 and the source and drain electrodes 57 and 59 are formed by entirely depositing a metal layer using a CVD technique or a sputtering technique and then patterning. After the source and drain electrodes 57 and 59 were patterned, the ohmic contact layer 53 at an area corresponding to the gate electrode 43 is patterned to expose the active layer 51. The area of the active layer 51 corresponding to the gate electrode 43 between the source and drain electrodes 57 and 59 makes a channel. The drain electrode 59 electrically contacts the pixel electrode 55 without any contact hole. The data line 63 and the source and drain electrodes 57 and 59 are made from chromium (Cr) or molybdenum (Mo).
Referring to FIG. 6D, a protective film 61 is provided at a TFT area. The protective film 61 forms by depositing an insulating material on the gate insulating layer 19 and then patterning it in such a manner to cover the source and drain electrodes 57 and 59. The protective film 61 is mainly made from an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx).
Such a liquid crystal display has an increased capacitance value of the storage capacitor so as to overcome the flicker phenomenon. Increasing the capacitance value of the storage capacitor requires increasing the area of the capacitor electrode. In other words, the LCD of storage on gate system should widen the width of the gate line so as to increase the capacitance value of the storage capacitor. However, since the aperture ratio is reduced and a line delay effect of a gate signal is enhanced when a width of the gate line is widened, there is a limit to widening the width of the gate line. Furthermore, since the LCD of storage on common system has the storage capacitor provided at the center of the pixel cell, this LCD has a smaller aperture ratio than a LCD of a storage on gate system.
As discussed above, as the area of the capacitor electrode increases, the aperture ratio is reduced. In particular, a high pixel density LCD, a ferroelectric LCD or a semi-ferroelectric LCD acquires high capacitance value of the storage capacitor while greatly reducing the aperture ratio. However, modern display technology requires enhanced capacitance while simultaneously maintaining or increasing the aperture ratio.